1. Field
The disclosed embodiments relate to the design of memories for computer systems. More specifically, the disclosed embodiments relate to a technique for offsetting clock package pins in a clamshell memory topology to improve signal integrity.
2. Related Art
Modern memory systems often provide separate pathways for command/address signals and data signals. For example, some memory systems provide a multi-drop “fly-by path” to rout command/address signals from a memory controller through multiple memory devices, and a separate “direct path” to communicate data signals directly between the memory controller and the memory devices. Some memory systems that provide a fly-by path have a “clamshell” configuration, wherein pairs of memory packages containing memory chips are located on opposite sides of each memory module.
In such clamshell fly-by topologies, the two memory packages that comprise a given pair of opposing memory packages typically tap into a signal line on the fly-by path (such as a clock line) at a single shared location, which is located toward the center of the memory packages. Moreover, the package pins used to carry such signals are typically also located toward the center of the memory packages to reduce associated stub lengths within the memory packages. However, tapping into a signal line at a single shared location effectively places a double load on the signal line at the shared location. This double-load can worsen reflections that increase attenuation at high frequencies, and these reflections can be problematic for high-speed clock signals used for data timing.
Hence, what is needed is a method and an apparatus for reducing such reflections in signal lines in clamshell fly-by topologies.